View W3HG128M64EEUXXXD4ISG_3307010.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w3hg128m64eeu-d4 march 2006 rev. 0 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 1gb C 128mx64 ddr2 sdram unbuffered, so-dimm description the w3hg128m64eeu is a 128mx64 double data rate 2 sdram memory module based on 1gb ddr2 sdram components. the module consists of eight 128mx8, in fbga package mounted on a 200 pin so-dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option features 200-pin, small-outline dimm (so-dimm), raw card "b" fast data transfer rates: pc2-6400*, pc2-5300*, pc2-4200 and pc2-3200 utilizes 800*, 667*, 533 and 400 mb/s ddr2 sdram components v cc = v ccq = 1.8v 0.1v v ccspd = 1.7v to 3.6v jedec standard 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option four-bit prefetch architecture dll to align dq and dqs transitions with ck multiple internal device banks for concurrent operation supports duplicate output strobe (rdqs/rdqs#) programmable cas# latency (cl): 3, 4, 5* and 6* adjustable data-output drive strength on-die termination (odt) posted cas# latency: 0, 1, 2, 3 and 4 serial presence detect (spd) with eeprom 64ms: 8,192 cycle refresh gold edge contacts single rank rohs compliant jedec package option ? 200 pin (so-dimm) ? pcb C 29.20mm (1.150") typ operating frequencies pc2-6400* pc2-5300* pc2-4200 pc2-3200 clock speed 400mhz 333mhz 266mhz 200mhz cl-t rcd -t rp 6-6-6 5-5-5 4-4-4 3-3-3 * consult factory for availability
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin names symbol description a0 - a13 address input odt0 on-die termination ck0, ck0# differential clock inputs ck1, ck1# differential clock inputs cke0 clock enable input cs0# chip select ras#, cas#, we# command inputs ba0 - ba2 bank address inputs dm0 - dm7 input data mask dq0 - dq63 data input/output dqs0 - dqs7 dqs0#-dqs7# data strobe scl serial clock for presence detect sa0-sa1 presence detect address inputs sda serial presence detect data v cc power supply v ref sstl_18 reference voltage v ss ground v ccspd serial eeprom power supply nc no connect pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 dqs2 101 a1 151 dq42 2v ss 52 dm2 102 a0 152 dq46 3v ss 53 v ss 103 v cc 153 dq43 4 dq4 54 v ss 104 v cc 154 dq47 5 dq0 55 dq18 105 a10/ap 155 v ss 6 dq5 56 dq22 106 ba1 156 v ss 7 dq1 57 dq19 107 ba0 157 dq48 8v ss 58 dq23 108 ras# 158 dq52 9v ss 59 v ss 109 we# 159 dq49 10 dm0 60 v ss 110 cs0# 160 dq53 11 dqs0# 61 dq24 111 v cc 161 v ss 12 v ss 62 dq28 112 v cc 162 v ss 13 dqs0 63 dq25 113 cas# 163 nc 14 dq6 64 dq29 114 odt0 164 ck1 15 v ss 65 v ss 115 nc 165 v ss 16 dq7 66 v ss 116 a13 166 ck1# 17 dq2 67 dm3 117 v cc 167 dqs6# 18 v ss 68 dqs3# 118 v cc 168 v ss 19 dq3 69 nc 119 nc 169 dqs6 20 dq12 70 dqs3 120 nc 170 dm6 21 v ss 71 v ss 121 v ss 171 v ss 22 dq13 72 v ss 122 v ss 172 v ss 23 dq8 73 dq26 123 dq32 173 dq50 24 v ss 74 dq30 124 dq36 174 dq54 25 dq9 75 dq27 125 dq33 175 dq51 26 dm1 76 dq31 126 dq37 176 dq55 27 v ss 77 v ss 127 v ss 177 v ss 28 v ss 78 v ss 128 v ss 178 v ss 29 dqs1# 79 cke0 129 dqs4# 179 dq56 30 ck0 80 nc 130 dm4 180 dq60 31 dqs1 81 v cc 131 dqs4 181 dq57 32 ck0# 82 v cc 132 v ss 182 dq61 33 v ss 83 nc 133 v ss 183 v ss 34 v ss 84 nc 134 dq38 184 v ss 35 dq10 85 ba2 135 dq34 185 dm7 36 dq14 86 nc 136 dq39 186 dqs7# 37 dq11 87 v cc 137 dq35 187 v ss 38 dq15 88 v cc 138 v ss 188 dqs7 39 v ss 89 a12 139 v ss 189 dq58 40 v ss 90 a11 140 dq44 190 v ss 41 v ss 91 a9 141 dq40 191 dq59 42 v ss 92 a7 142 dq45 192 dq62 43 dq16 93 a8 143 dq41 193 v ss 44 dq20 94 a6 144 v ss 194 dq63 45 dq17 95 v cc 145 v ss 195 sda 46 dq21 96 v cc 146 dqs5# 196 v ss 47 v ss 97 a5 147 dm5 197 scl 48 v ss 98 a4 148 dqs5 198 sa0 49 dqs2# 99 a3 149 v ss 199 v ccspd 50 nc 100 a2 150 v ss 200 sa1
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram a0 serial pd a1 a2 sa0 sa1 sda scl wp v ccspd v cc v ref v ss serial pd ddr2 sdrams ddr2 sdrams ddr2 sdrams, eeprom cs0# 3? dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq dq dq dq dq dq dq dq dqs0# dqs0 dm0 dm cs# dqs dqs# dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq dq dq dq dq dq dq dq dqs4# dqs4 dm4 dm cs# dqs dqs# dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq dq dq dq dq dq dq dq dqs1# dqs1 dm1 dm cs# dqs dqs# dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq dq dq dq dq dq dq dq dqs5# dqs5 dm5 dm cs# dqs dqs# dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq dq dq dq dq dq dq dq dqs2# dqs2 dm2 dm cs# dqs dqs# dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq dq dq dq dq dq dq dq dqs6# dqs6 dm6 dm cs# dqs dqs# dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq dq dq dq dq dq dq dq dqs3# dqs3 dm3 dm cs# dqs dqs# dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq dq dq dq dq dq dq dq dqs7# dqs7 dm7 dm cs# dqs dqs# ba0-ba2 a0-a13 ras# cas# we# cke0 odt0 ba0-ba2: ddr2 sdrams a0-a13: ddr2 sdrams ras#: ddr2 sdrams cas#: ddr2 sdrams we#: ddr2 sdrams cke0: ddr2 sdrams odt0: ddr2 sdrams 3? ddr2 sdrams x 4 ck0 ck0# ddr2 sdrams x 4 ck1 ck1# 100? 100? note: 1. all resistor values are 22 ohm unless otherwise speci? ed.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs recommended dc operating conditions all voltages referenced to v ss parameter symbol min max units notes supply voltage v cc 1.7 1.9 v - i/o reference voltage v ref 0.49 x v cc 0.51 x v cc v1 i/o termination voltage (system) v tt v ref - 40 v ref + 40 mv 2 note: 1. v ref is expected to equal v ccq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref (dc). this measurement is to be taken at the nearest v ref bypass capacitor. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . absolute maximum dc characteristics symbol parameter min max units v cc v cc supply voltage relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 c t case ddr2 sdram device operating temperature* 0 85 c t opr operating temperature (ambient) 0 65 c i i input leakage current; any input 0v v in v cc ; v ref input 0v v in 0.95v; (all other pins not under test = 0v) command/address, ras#, cas#, we# s#, cke -40 40 a ck, ck# -20 20 dm -5 5 i oz output leakage current; 0v v out v cc q; dqs and odt are disabled dq, dqs, dqs# -5 5 a i vref v ref leakage current; v ref = valid v ref level -16 16 a * t case speci? es as the temperature at the top center of the memory devices. capacitance t a = 25c, f = 100mhz, v cc = 1.8v, v ref = v ss parameter symbol max unit input capacitance (a0-a12) c in1 35 pf input capacitance (ras#,cas#,we#) c in2 35 pf input capacitance (cke0) c in3 31 pf input capacitance (ck0, ck0#) c in4 15 pf input capacitance (cs0#) c in5 31 pf input capacitance (dqs0#-dqs17#) c in6 6pf input capacitance (ba0-ba1) c in7 35 pf data input/output capacitance (dq0-dq63) c out 6pf note: * these capacitance values are based on worst case component values in conjunction with the circuit boards associated parasitic net capacitance.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 i cc specifications and conditions ddr2 sdram components only v cc = +1.8v 0.1v parameter symbol condition 806 665 534 403 units operating one device bank active-precharge current; i cc0 t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. tbd 800 640 640 ma operating one device bank active-read- precharge current; i cc1 i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min (i cc ), t rcd = t rcd (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc4w . tbd 1,160 760 760 ma precharge power-down current; i cc2p all device banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. tbd 56 40 40 ma precharge quiet standby current; i cc2q all device banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating. tbd 480 328 280 ma precharge standby current; i cc2n all device banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching. tbd 520 360 280 ma active power-down current; i cc3p all device banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. fast pdn exit mr[12] = 0 tbd 320 240 200 ma slow pdn exit mr[12] = 1 tbd 80 80 80 ma active standby current; i cc3n all device banks open; t ck = t ck (i cc ), t ras = t ras max (i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. tbd 560 400 320 ma operating burst write current; i cc4w all device banks open, continuous burst writes; bl = 4, cl = cl (i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max (i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. tbd 1,440 1,040 960 ma operating burst read current; i cc4r all device banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max (i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. tbd 1,640 1,160 1,080 ma burst refresh current; i cc5 t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. tbd 2,160 2,000 1,920 ma self refresh current; i cc6 ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating. tbd 56 40 40 ma operating device bank interleave read current; i cc7 all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i cc ), al = t rcd (i cc )-1 x t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = t rcd (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching tbd 2,720 2,360 2,360 ma note: ? i cc speci? cation is based on micron components. other dram manufacturers speci? cation may be different.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac operating conditions v cc = +1.8v 0.1v clock ac characteristics symbol 806 665 534 403 units notes parameter min max min max min max min max clock cycle time cl = 6 t ck (6) 3,000 8,000 ------ps cl = 5 t ck (5) 3,000 8,000 3,000 8,000 ----ps 16, 22, 36, 38 cl = 4 t ck (4) 3,000 8,000 3,750 8,000 3,750 8,000 5,000 8,000 ps cl = 3 t ck (3) - - 5,000 8,000 5,000 8,000 5,000 8,000 ps ck high-level width t ch avg 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck 45 ck low-level width t cl avg 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t ck half clock period t hp min ( t ch, t cl) min ( t ch, t cl) min ( t ch, t cl) min ( t ch, t cl) ps 46 clock (absolute) absolute tck t ck abs t ckavg+ (min)+ t jitper (min) t ckavg+ (max)+ t jitper (max) t ckavg+ (min)+ t jitper (min) t ckavg+ (max)+ t jitper (max) t ckavg+ (min)+ t jitper (min) t ckavg+ (max)+ t jitper (max) t ckavg+ (min)+ t jitper (min) t ckavg+ (max)+ t jitper (max) ps absolute ck high-level width t ch abs t ckavg (min)* t ch avg+ t jit dty(min) t ckavg (max)* t ch avg+ t jit dty(max) t ckavg (min)* t ch avg+ t jit dty(min) t ckavg (max)* t ch avg+ t jit dty(max) t ckavg (min)* t ch avg+ t jit dty(min) t ckavg (max)* t ch avg+ t jit dty(max) t ckavg (min)* t ch avg+ t jit dty(min) t ckavg (max)* t ch avg+ t jit dty(max) ps absolute ck low-level width t cl abs t ckavg (min)* t clavg (min)+ t jit dty(min) t ckavg (max)* t clavg (max)+ t jit dty(min) t ckavg (min)* t clavg (min)+ t jit dty(min) t ckavg (max)* t clavg (max)+ t jit dty(min) t ckavg (min)* t clavg (min)+ t jit dty(min) t ckavg (max)* t clavg (max)+ t jit dty(min) t ckavg (min)* t clavg (min)+ t jit dty(min) t ckavg (max)* t clavg (max)+ t jit dty(min) ps clock jitter clock jitter - period t jit per -125 125 -125 125 -125 125 -125 125 ps 39 clock jitter - half period t jit duty -125 125 -125 125 -125 125 -150 150 ps 40 clock jitter - cycle to cycle t jit cc 250 250 250 250 ps 41 cumulative jitter error, 2 cycles t err 2per -175 175 -175 175 -175 175 -175 175 ps 42 cumulative jitter error, 3 cycles t err 3per -225 225 -225 225 -225 225 -225 225 ps 42 cumulative jitter error, 4 cycles t err 4per -250 250 -250 250 -250 250 -250 250 ps 42 cumulative jitter error, 5cycles t err 5per -250 250 -250 250 -250 250 -250 250 ps 42, 48 cumulative jitter error, 6-10 cycles t err 6-10per -350 350 -350 350 -350 350 -350 350 ps 42, 48 cumulative jitter error, 11-50 cycles t err 11-50per -450 450 -450 450 -450 450 -450 450 ps 42 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac operating conditions (continued) v cc = +1.8v 0.1v data ac characteristics symbol 806 665 534 403 units notes parameter min max min max min max min max t qhs - 340 - 340 - 400 - 450 ps 47 dq output access time from ck/ck# t ac -450 +450 -450 +450 -500 +500 -600 +600 ps 43 data-out high-impedance window from ck/ck# t hz t ac (max) t ac (max) t ac (max) t ac (max) ps 8, 9, 43 data-out low-impedance window from ck/ck# t lz1 t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) ps 8, 10, 43 data-out low-impedance window from ck/ck# t lz 2 2* t ac (min) t ac (max) 2* t ac (min) t ac (max) 2* t ac (min) t ac (max) 2* t ac (min) t ac (max) ps 8, 10, 43 dq and dm input setup time relative to dqs t ds a 300 300 350 400 ps 7, 15, 19 dq and dm input hold time relative to dqs t dh a 300 300 350 400 ps 7, 15, 19 dq and dm input setup time relative to dqs t ds b 100 100 100 150 ps 7, 15, 19 dq and dm input hold time relative to dqs t dh b 175 175 225 275 ps 7, 15, 19 dq and dm input pulse width (for each input) t dipw 0.35 0.35 0.35 0.35 t ck 37 data hold skew factor t qhs 340 340 400 450 ps 47 dqCdqs hold, dqs to ? rst dq to go nonvalid, per access t qh t hp- t qhs t hp- t qhs t hp- t qhs t hp- t qhs ps 15, 17, 47 data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 15, 17 data strobe dqs input high pulse width t dqsh 0.35 0.35 0.35 0.35 t ck 37 dqs input low pulse width t dqsl 0.35 0.35 0.35 0.35 t ck 37 dqs output access time from ck/ck# t dqsck -400 +400 -400 +400 -450 +450 -500 +500 ps 40 dqs falling edge to ck rising C setup time t dss 0.2 0.2 0.2 0.2 t ck 37 dqs falling edge from ck rising C hold time t dsh 0.2 0.2 0.2 0.2 t ck 37 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac operating conditions (continued) v cc = +1.8v 0.1v data strobe ac characteristics symbol 806 665 534 403 units notes parameter min max min max min max min max dqsCdq skew, dqs to last dq valid, per group, per access t dqsq 240 240 300 350 ps 15, 17 dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ck 33, 37, 43 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 33, 34, 37, 43 dqs write preamble setup time t wpres0000ps12, 13, dqs write preamble t wpre 0.35 0.35 0.25 0.25 t ck 37 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t ck 11, 37 positive dqs latching edge to associated clock edge t dqss - 0.25 0.25 - 0.25 0.25 - 0.25 0.25 - 0.25 0.25 t ck 37 write command to ? rst dqs latching transition wl- t dqss wl+ t dqss wl- t dqss wl+ t dqss wl- t dqss wl+ t dqss wl- t dqss wl+ t dqss t ck command and address address and control input pulse width for each input t ipw 0.6 0.6 0.6 0.6 t ck 37 address and control input setup time t is a 400 400 500 600 ps 6, 19 address and control input hold time t ih a 400 400 500 600 ps 6, 19 address and control input setup time t is b 200 200 250 350 ps 6, 19 address and control input hold time t ih b 275 275 375 475 6, 19 cas# to cas# command delay t ccd2222 t ck 37 active to active (same bank) command t rc 54 55 55 55 ns 31, 37 active bank a to active bank b command t rrd (x8) 7.5 7.5 7.5 7.5 ns 25, 37 active to read or write delay t rcd12151515 ns37 four bank activate period t faw (x8) 37.5 37.5 37.5 37.5 ns 28, 37 active to precharge command t ras 40 70,000 40 70,000 40 70,000 40 70,000 ns 18, 31, 37 internal read to precharge command delay t rtp 7.5 7.5 7.5 7.5 ns 21, 25. 37 write recovery time t wr 15 15 15 15 ns 25, 37 auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp t wr + t rp t wr + t rp ns 20 internal write to read command delay t wtr 7.5 7.5 7.5 10 ns 25, 37 precharge command period t rp 12 15 15 15 ns 29, 37 precharge all command period t rpa t rp + t ck t rp + t ck t rp + t ck t rp + t ck ns 29 load mode command cycle time t mrd2222 t ck 37 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac operating conditions (continued) v cc = +1.8v 0.1v ac characteristics symbol 806 665 534 403 units notes parameter min max min max min max min max refresh cke low to ck,ck# uncertainty t delay t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih ns 26 refresh to active or refresh to refresh command interval t rfc 127.5 70,000 127.5 70,000 127.5 70,000 127.5 70,000 ns 14, 37 average periodic refresh interval (commercial) t refi 7.8 7.8 7.8 7.8 s 14, 37 average periodic refresh interval (industrial) t refi it 3.9 3.9 3.9 3.9 s 14, 37 self refresh exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 200 200 t ck 37 exit self refresh timing reference t isxr t is t is t is t is ps 6, 27 odt odt turn-on delay t aond22222222 t ck 37 odt turn-on t aond t ac (min) t ac (max) + 700) t ac (min) t ac (max) + 700) t ac (min) t ac (max) + 1,000) t ac (min) t ac (max) + 1,000) ps 23, 43 odt turn-off delay t aofd 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 t ck 35, 37 odt turn-off t aof t ac (min) t ac (max + 600) t ac (min) t ac (max + 600) t ac (min) t ac (max + 600) t ac (min) t ac (max + 600) ps 24, 44 odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd3333 t ck 37 odt power-down exit latency t axpd8888 t ck 37 odt enable from mrs command t mod 12 12 12 12 ns 37, 49 power down exit active power-down to read command, mr[bit12=0] t xard2222 t ck 37 exit active power-down to read command, mr[bit12=1] t xards 7 - al 7 - al 6 - al 6 - al 37 exit precharge power-down to any non-read command. t xp2222 t ck 37 cke minimum high/low time t cke3333 t ck 32, 37 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cations may be different.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced* 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs notes: 1. all voltages referenced to vss. 2. tests for ac timing, i cc , and electrical ac and dc characteristics may be conducted at nominal reference / supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed. odt is disabled for all measurements that are not odt-speci? c. 3. outputs measured with equivalent load: 4. ac timing and i cc tests may use a v il -to-v ih swing of up to 1.0v in the test environment and parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the slew rate for the input signals used to test the device is 1.0v/ns for signals in the range between v il (ac) and v ih (ac). slew rates less than 1.0v/ns require the timing parameters to be derated as speci? ed. 5. the ac and dc input level speci? cations are as de? ned in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. there are two sets of values listed for command/address: t isa , t iha and t isb , t ihb . the t isa , t iha values (for reference only) are equivalent to the baseline values of t isb , t ihb at v ref when the slew rate is 1v/ns. the baseline values, t isb , t ihb , are the jedec de? ned values, referenced from the logic trip points. t isb is referenced from v ih (ac) for a rising signal and v il (ac) for a falling signal, while t ihb is referenced from v il (dc) for a rising signal and v ih (dc) for a falling signal. if the command/address slew rate is not equal to 1 v/ns, then the baseline values must be derated. 7. the values listed are for the differential dqs strobe (dqs and dqs#) with a differential slew rate of 2 v/ns (1 v/ns for each signal). there are two sets of values listed: t dsa. t dha and t dsb, t dhb. the t dsa, t dha values (for reference only) are equivalent to the baseline values of t dsb, t dhb at v ref when the slew rate is 2 v/ns, differentially. the baseline values, t dsb, t dhb, are the jedec-de? ned values, referenced from the logic trip points. t dsb is referenced from v ih (ac) for a rising signal and v il (ac) for a falling signal, while t dsb is referenced from v il (dc) for a rising signal and v ih (dc) for a falling signal. if the differential dqs slew rate is not equal to 2 v/ns, then the baseline values must be derated. if the dqs differential strobe feature is not enabled, then the dqs strobe is single-ended, the baseline values not applicable, and timing is not referenced to the logic trip points. single- ended dqs data timing is referenced to dqs crossing v ref . 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 9. this maximum value is derived from the referenced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition 11. the intent of the "dont care" state after completion of the postamble is the dqs- driven signal should either be high, low or high-z and that any signal transition within the input switching region must follow valid input requirements. that is if dqs transitions high (above v ih dc(min) then it must not transition low (below v ih (dc) prior to t dqsh(min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms (commercial) or 32ms (industrial). this equates to an average refresh rate of 7.8125s (commercial) or 3.9607s (industrial). however, a refresh command must be asserted at least once every 70.3s or t rfc (max). to ensure all rows of all banks are properly refreshed, 8,192 refresh commands must be issued every 64ms. 15. referenced to each output group: x4 = dqs with dq0Cdq3; x8 = dqs with dq0Cdq7; x16 = ldqs with dq0Cdq7; and udqs with dq8Cdq15. 16. ck and ck# input slew rate is referenced at 1 v/ns (2 v/ns if measured differentially). 17. the data valid window is derived by achieving other speci? cations - t hp. ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. reads and writes with auto precharge are allowed to be issued before t ras(min) is satis? ed since t ras lockout feature is supported in ddr2 sdram. 19. v il /v ih ddr2 overshoot/undershoot. 20. t dal = (nwr) + ( t rp/ t ck). each of these terms, if not already an integer, should be rounded up to the next integer. t ck refers to the application clock period; nwr refers with t wr programmed to four clocks would have t dal = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks = 8 clocks. 21. the minimum internal read to precharge time. this is the time from the last 4-bit prefetch begins to when the precharge command can be issued. a 4-bit prefetch is when the read command internally latches the read so that data will output cl later. this parameter is only applicable when t rtp/(2x t ck) > 1, such as frequencies faster than 533 mhz when trtp = 7.5ns. if trtp/ (2x t ck) 1, then equation al + bl/2 applies. tras (min) also has to be satis? ed as well. the ddr2 sdram will automatically delay the internal precharge command until t ras (min) has been satis? ed. 22. operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. 23. t dal = (nwr) + ( t rp/ t ck): for each of the terms above, if not already an integer, round to the next highest integer. t ck refers to the application clock period; ac operation condition notes: nwr refers to the t wr parameter stored in the mr[11,10,9]. example: for -533mb/s at t ck = 3.75 ns with t wr programmed to four clocks. t dal = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks. 24. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high-z. both are measured from t aofd. 25. this parameter has a two clock minimum requirement at any t ck. 26. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. 27. t isxr is equal to t is and is used for cke setup time during self refresh exit. 28. no more than 4 bank active commands may be issued in a given t faw(min) period. t rrd(min) restriction still applies. the t faw(min) parameter applies to all 8 bank ddr2 devices, regardless of the number of banks already open or closed. 29. t rpa timing applies when the precharge(all) command is issued, regardless of the number of banks already open or closed. if a single-bank precharge command is issued, t rp timing applies. t rpa(min) applies to all 8-bank ddr2 devices. 30. value is minimum pulse width, not the number of clock registrations. 31. this is applicable to read cycles only. write cycles generally require additional time due to t wr during auto precharge. 32. t cke (min) of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 x t ck + t ih. 33. this parameter is not referenced to a speci? c voltage level, but speci? ed when the device output is no longer driving ( t rpst) or beginning to drive ( t rpre). 34. when dqs is used single-ended, the minimum limit is reduced by 100ps. 35. the half-clock of t aofd's 2.5 t ck assumes a 50/50 clock duty cycle. this half-clock value must be derated by the amount of half-clock duty cycle error. for example, if the clock duty cycle was 47/53, t aofd would actually be 2.5 - 0.03, or 2.47 for t aof (min) and 2.5 + 0.03 or 2.53 for t aof (max). 36. the clocks t ck avg is the average clock over any 200 consecutive clocks and output (v out ) reference point 25? v tt = v cc q /2
w3hg128m64eeu-d4 march 2006 rev. 0 advanced* 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs t ck avg (min) is the smallest clock rate allowed, except a deviation due to allowed clock jitter. input clock jitter is allowed provided it does not exceed values speci? ed. also, the jitter must be of a random gaussian distribution in nature. 37. the inputs to the dram must be aligned to the associated clock; that is, the actual clock that latches it in. however, the input timing (in ns) references to the t ck avg when determining the required number of clocks. the following input parameters are determined by taking the speci? ed percentage times the tckavg rather thank t ck: t ipw, t dipw, t dqss, t dqsh, t dqsl, t dss, t dh, t wpst, and t wpre. 38. spread spectrum is not included in the jitter speci? cation values. however, the input clock can accommodate spread spectrum at a sweep rate in the range 20C60 khz with additional one percent of t ck avg as a long-term jitter component; however, the spread spectrum may not use a clock rate below t ck avg (min) or above t ck avg (max). 39. the period jitter ( t jit per ) is the maximum deviation in the clock period from the average or nominal clock allowed in either the positive or negative direction. jedec speci? es tighter jitter numbers during dll locking time. during dll lock time, the jitter values should be 20 percent less than noted in the table (dll locked). 40. the half-period jitter ( t jit dty ) applies to either the high pulse of clock or the low pulse of clock; however, the two cumulatively can not exceed t jit per . 41. the cycle-to-cycle jitter ( t jit cc ) is the amount the clock period can deviate from one cycle to the following cycle. jedec speci? es tighter jitter numbers during dll locking time. during dll lock time, the jitter values should be 20 percent less than noted in the table (dll locked). 42. the cumulative jitter error ( t err nper ) where n is 2, 3, 4, 5, 6C10, or 11C50, is the amount of clock time allowed to consecutively accumulate away from the average clock over any number of clock cycles. 43. the dram output timing is aligned to the nominal or average clock. most output parameters must be derated by the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. the following parameters are required to be derated by subtracting t err 5per (max): t ac(min), t dqsck(min), t hz(min), t lz dq (min), t aon(min); while these following parameters are required to be derated by subtracting t err 5per (min): t ac(max), t dqsck(max), t hz(max), t lz dq (max), t aon(max). the parameter t rpre(min) is derated by subtracting t jitper(max), while t prpe(max), is derated by subtracting t jit per (max) . the parameter t rpst(max), is dated by subtracting t jit dty (min). 44. half-clock output parameters must be derated by the actual t err 5per and t jit dty when input clock jitter is present; this will result in each parameter becoming larger. the parameter t aof(min) is required to be derated by subtracting both t err 5per (max) and t jit per (max). the parameter t aof(max) is required to be derated by subtracting both t err 5per (min) and t jit dty (min). 45. min( t cl, t ch) refers to the smaller of the actual clock low time and the actual clock high time driven to the device. the clock's half period must also be of a gaussian distribution; t ch avg and t cl avg must be met with or with our clock jitter and with or without duty cycle jitter. t ch avg and t cl avg are the average of any 200 consecutive ck falling edges. 46. t hp (min) is the lesser of t cl and t ch actually applied to the device ck and ck# inputs; thus, t hp(min) the lesser of t cl abs (min) and t ch abs (min). 47. t qh = t hp - t qhs; the worst case t qh would be the smaller of t cl abs (max) or t ch abs (max) times t ck abs (min) - t qhs. minimizing the amount of t ch avg offset and value of t jit dty will provide a larger t qh, which in turn will provide a larger valid data out window. 48. jedec speci? es using t err 6-10per when derating clock-related output timing (notes 43C44). micron requires less derating by allowing t err 5per to be used. 49. requires 8 t ck for backward compatibility.
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 3.80 (0.150) max pin 1 67.75 (2.667) max 20.00 (0.787) typ 1.80 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ 2.00 (0.079) r (2x) pin 199 pin 200 pin 2 front view 2.15 (0.085) 6.00 (0.236) 63.60 (2.504) typ 2.54 (0.100) 0.99 (0.039) typ 29.20 (1.150) typ back view 1.10 (0.043) max 47.4 (1.87) typ 11.4 (0.45) typ 4.2 (0.165) typ package dimensions for d4 * all dimensions are in millimeters and (inches) ordering information for d4 part number clock/data rate frequency cas latency t rcd t rp height* w3hg128m64eeu806d4xxg** 400mhz/800mb/s 6 6 6 29.20mm (1.150") typ w3hg128m64eeu665d4xxg* 333mhz/667mb/s 5 5 5 29.20mm (1.150") typ w3hg128m64eeu534d4xxg 266mhz/533mb/s 4 4 4 29.20mm (1.150") typ w3hg128m64eeu403d4xxg 200mhz/400mb/s 3 3 3 29.20mm (1.150") typ ** consult factory for availability notes: ? rohs product. ("g" = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult f actory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide w 3 h g 128m 64 e e u xxx d4 x x g wedc memory (sdram) ddr 2 gold depth bus width component width x8 1.8v unbuffered data rate (mb/s) package 200 pin industrial temp option (for commercial leave "blank" for industrial add "i") component vendor name (m = micron) (s = samsung) g = rohs compliant
w3hg128m64eeu-d4 march 2006 rev. 0 advanced 14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 1gb C 128mx64 ddr2 sdram unbuffered dram die options: ? samsung: a-die, will move to b-die q3'06 ? micron: u38a:a, will move to u38z:d q4'06, and u48b:e q2'07 revision history rev # history release date status rev 0 created 3-06 advanced rev 1 1.0 update part number guide 1.2 added indicator "x" in part number for industrial temp option 1.3 added dram die option 4-06 advanced

▲Up To Search▲

Price & Availability of W3HG128M64EEUXXXD4ISG

	To Download W3HG128M64EEUXXXD4ISG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .